This invention relates to methods of manufacture of semiconductor integrated circuit devices, and more particularly to a method of determining across-wafer critical dimension uniformity performance during wafer processing, using optical endpoint detection.
In the manufacture of VLSI devices, critical dimension uniformity is crucial to the overall electrical performance of the devices being made. If the nominal line width for a transistor gate or the like is 0.5 micron, then the actual line width in the finished device should be exactly that, and should be the same for all devices within a wafer, and all wafers within a lot. Variations in critical dimension uniformity are excursions from the desired process, and cause reductions in chip manufacturing efficiency (yield) and in final chip performance. Thus, in the semiconductor industry a very important factor is the monitoring and controlling of critical dimension uniformity.
The ability to determine critical dimension uniformity performance previously has been restricted to direct measurement systems (i.e., scanning electron microscopes or SEMs, optical microscopes, electrical probers, etc.), all of which required significant additional process time. Due to this added process time, typically only a sample of measurements were (and still are) performed to determine wafer-to-wafer, lot-to-lot, and across-wafer critical dimension performance. As a result, most wafers were processed and transferred on to the next process step without having their critical dimension performance determined. This lack of 100% critical dimension determination allows potentially out-of-specification wafers to be transferred on, only to be scrapped for poor electrical performance at final wafer probe. This significantly adds to the inefficiency and cost of chip manufacturing.
An optical end point detector (OEPD) has been developed to monitor and control wafer-to-wafer and lot-to-lot critical dimension uniformity performance. The technology of optical endpoint detectors is described in the following publications: (1) S. Grindle and E. Pavelcheck, "Photoresist Characterization Using Interferometry During Development," Proceedings of the 4th Annual Test and Measurement World Expo, San Jose, Calif., 14-16 May 1985; (2) M. Thomson, "In-situ Develop End Point Control to Eliminate CD Variance," SPIE Proceedings of Integrated Circuit Metrology, Inspection, and Process Control IV, San Jose, Calif., 5-6 Mar. 1990; (3) K. M. Sautter, M. Ha, and T. Batchelder, "Development Process Control and Optimization Utilizing an End Point Monitor," KTI Interface '88 Proceedings; and (4) L. J. Uhler, "Automatic Linewidth Control System," SPIE Proceedings of Integrated Circuit Metrology, Inspection, and Process Control, San Jose, Calif., 1987. These optical endpoint detectors operate by directing a source of light at single area of developing photoresist, and observing interference patterns caused by the light reflecting from the top of the photoresist and also from the substrate. This equipment has provided much-improved monitoring and control of critical dimension uniformity.
However, even with use of optical endpoint detectors, across-wafer critical dimension performance is still an unknown, such that direct measurement systems are still required. It is proposed herein to enhance the wafer-to-wafer and lot-to-lot technique by providing the capability to monitor across-wafer critical dimension uniformity performance by simultaneously monitoring multiple sites across a wafer for optical endpoint detections.
If across-wafer critical dimension uniformity performance could be provided, a number of benefits would be realized: (1) the capability to determine across-wafer critical dimension performance in-situ for all wafers processed rather than for only sample wafers; (2) the reduction or elimination of out-of-specification wafers being transferred on to later process steps undetected; (3) the reduction or elimination of after-process direct critical dimension measurements using SEMs or the like; (4) an increase in chip manufacturing efficiency; and (5) a decrease in chip manufacturing cost.
It is proposed, therefore, to provide a way of allowing the determination of across-wafer critical dimension uniformity performance during the actual processing of the wafer, rather than after the processing is completed. Also this information should be determined for every wafer processed, not just samples, without requiring direct critical dimension measurement. This would increase overall efficiency of wafer processing by reducing total inspection time through selective inspection of flagged wafers, as well as the reduction or elimination of after-process critical dimension measurements. Also, this would enable the reduction of capital expenditures for critical dimension measurement systems.
Currently, the ability to determine across-wafer critical dimension uniformity performance is limited to direct measurements taken after processing is completed. No currently used equipment allows determination of across-wafer critical dimension uniformity performance while the wafer is being processed. Also, while the optical endpoint detectors such as discussed in the publications referred to above have the ability to predict and control wafer-to-wafer and lot-to-lot critical dimensions, they do not maintain the capacity to predict across-wafer critical dimension uniformity performance. Therefore, with current technology, prior to this invention, there is no capability for across-wafer critical dimension uniformity performance determination using optical endpoint detectors.